rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg438f/adg439f* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 high performance 4/8 channel fault-protected analog multiplexers functional block diagrams s1 s8 a0 d a1 a2 en adg438f 1 of 8 decoder a0 adg439f a1 en s1a da s4a s1b s4b db 1 of 4 decoder features fast switching times t on 250 ns max t off 150 ns max fault and overvoltage protection (C40 v, +55 v) all switches off with power supply off analog output of on channel clamped within power supplies if an overvoltage occurs latch-up proof construction break before make construction ttl and cmos compatible inputs applications data acquisition systems industrial and process control systems avionics test equipment signal routing between systems high reliability control systems general description the adg438f/adg439f are cmos analog multiplexers, the adg438f comprising 8 single channels and the adg439f comprising four differential channels. these multiplexers pro- vide fault protection. using a series n-channel, p-channel, n- channel mosfet structure, both device and signal source protection is provided in the event of an overvoltage or power loss. the multiplexer can withstand continuous overvoltage inputs from C40 v to +55 v. during fault conditions, the multi- plexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. this protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources which drive the multiplexer. the adg438f switches one of eight inputs to a common out- put as determined by the 3-bit binary address lines a0, a1 and a2. the adg439f switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. an en input on each device is used to enable or disable the device. when disabled, all channels are switched off. product highlights 1. fault protection. the adg438f/adg439f can withstand continuous volt- age inputs up to C40 v or +55 v. when a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nano- amperes flows. 2. on channel turns off while fault exists. 3. low r on. 4. fast switching times. 5. break-before-make switching. switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. trench isolation eliminates latch-up. a dielectric trench separates the p- and n-channel mosfets thereby preventing latch-up. 7. improved off isolation. trench isolation enhances the channel-to-channel isolation of the adg438f/adg439f. *patent pending.
C2C rev. c adg438f/adg439fCspecifications 1 dual supply b version C40 8 c to C40 8 c to parameter +25 8 c +85 8 c +105 8 c units test conditions/comments analog switch analog signal range v ss + 1.2 v ss + 1.2 v min v dd C 0.8 v dd C 0.8 v max r on 400 400 w max C10 v < v s < +10 v, i s = 1 ma; d r on 5 5 % max C5 v < v s < +5 v, i s = 1 ma; r on drift 0.6 %/ c typ v s = 0 v, i s = 1 ma r on match 3 3 3 % max v s = 10 v, i s = 1 ma leakage currents source off leakage i s (off) 0.01 na typ v d = 10 v, v s = 7 10 v; 0.5 2 5 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v d = 10 v, v s = 7 10 v; adg438f 0.5 5 30 na max test circuit 3 adg439f 0.5 5 15 na max channel on leakage i d , i s (on) 0.01 na typ v s = v d = 10 v; adg438f 0.5 5 30 na max test circuit 4 adg439f 0.5 5 15 na max fault output leakage current 0.02 na typ v s = C33 v, +33 v or +50 v, v d = 0 v, test circuit 3 (with overvoltage) 0.1 2 10 m a max input leakage current 0.005 m a typ v s = 25 v, v d = 7 10 v, test circuit 5 (with overvoltage) 0.1 1 2 m a max input leakage current 0.001 m a typ v s = 25 v, v d = v en = a0, a1, a2 = 0 v (with power supplies off) 0.1 1 4 m a max test circuit 6 digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 1 1 m a max v in = 0 or v dd c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 170 ns typ r l = 1 m w , c l = 35 pf; 220 300 320 ns max v s1 = 10 v, v s8 = 7 10 v; test circuit 7 t open 10 10 10 ns min r l = 1 k w , c l = 35 pf; v s = +5 v; test circuit 8 t on (en) 200 ns typ r l = 1 k w , c l = 35 pf; 250 300 300 ns max v s = +5 v; test circuit 9 t off (en) 110 ns typ r l = 1 k w , c l = 35 pf; 150 180 180 ns max v s = +5 v; test circuit 9 t sett , settling time 0.1% 0.5 0.5 m s typ r l = 1 k w , c l = 35 pf; 0.01% 1.7 1.7 m s typ v s = +5 v charge injection 4 pc typ v s =0v,r s =0 w ,c l = 1 nf; test circuit 10 off isolation 80 db typ r l = 1 k w , c l = 15 pf, f = 100 khz; v s = 7 v rms; test circuit 11 channel-to-channel crosstalk 85 db typ r l = 1 k w , c l = 15 pf, f = 100 khz; v s = 7 v rms; test circuit 12 c s (off) 5 pf typ c d (off) adg438f 50 pf typ adg439f 25 pf typ power requirements i dd 0.05 ma typ v in = 0 v or 5 v 0.15 0.25 0.25 ma max i ss 0.01 ma typ 0.02 0.04 0.04 ma max notes 1 temperature range is as follows: b version: C40 c to +105 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +15 v, v ss = C15 v, gnd = 0 v, unless otherwise noted)
adg438f/adg439f C3C rev. c absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C25 v v en , v a digital input . . . . . . . C 0.3 v to v dd + 2 v or 20 ma, whichever occurs first v s , analog input overvoltage with power on . . . . . v ss C 25 v to v dd + 40 v v s , analog input overvoltage with power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 v to +55 v continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 20 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle max) . . . . . . . . . . . 40 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 117 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +260 c soic package q ja , thermal impedance narrow body . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 c/w wide body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. table i. adg438f truth table a2 a1 a0 en on switch xxx0 none 00011 00112 01013 01114 10015 10116 11017 11118 x = dont care table ii. adg439f truth table a1 a0 en on switch pair x x 0 none 0011 0112 1013 1114 x = dont care adg438f/adg439f pin configurations dip/soic dip/soic a0 en a1 a2 s2 s3 s4 s5 s6 s7 s1 gnd v dd ds8 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) adg438f v ss a0 en a1 gnd s2a s3a s4a s2b s3b s4b v ss s1a v dd s1b da db 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) adg439f caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg438f/adg439f features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic dischar ges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package option* adg438fbn C40 c to +105 c n-16 ADG438FBRN C40 c to +105 c r-16n adg439fbn C40 c to +105 c n-16 adg439fbrn C40 c to +105 c r-16n adg439fbrw C40 c to +105 c r-16w *n = plastic dip; rn = 0.15" small outline ic (soic); rw = 0.3" small outline ic (soic). warning! esd sensitive device
adg438f/adg439f C4C rev. c terminology v dd most positive power supply potential. v ss most negative power supply potential. gnd ground (0 v) reference. r on ohmic resistance between d and s. d r on r on variation due to a change in the analog input voltage with a constant load current. r on drift change in r on when temperature changes by one degree celsius. r on match difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminals d, s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t open off time measured between 80% points of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current. typical performance graphs 2000 1000 0 C15 C5 15 5 010 C10 500 1750 1500 1250 750 250 v d (v s ) C volts r on C v t a = +25 8 c v dd = +5v v ss = C5v v dd = +10v v ss = C10v v dd = +15v v ss = C15v figure 1. on resistance as a function of v d (v s ) 1m 1 m 1p C50 C30 50 10 C20 20 C40 1n 30 40 100 m 10 m 10n 100n 10p 100p C10 0 v in C input voltage C volts i s C input leakage C a operating range v dd = 0v v ss = 0v v d = 0v 60 figure 2. i nput leakage current as a function of v s (power supplies off) during overvoltage conditions 1m 1 m 1p C50 C30 50 10 C20 20 C40 1n 30 40 100 m 10 m 10n 100n 10p 100p C10 0 v in C input voltage C volts i d C output leakage C a operating range v dd = +15v v ss = C15v v d = 0v 60 figure 3. output leakage current as a function of v s (power supplies on) during overvoltage conditions
adg438f/adg439f C5C rev. c 100 10 0.01 25 45 65 55 75 35 85 95 105 1 0.1 temperature C 8 c leakage currents C na i s (off) i d (off) i d (on) v dd = +15v v ss = C15v v d = +10v v s = C10v figure 7. leakage currents as a function of temperature 260 240 100 10 15 12 13 11 120 14 t on (en) v in = +2v 220 200 180 160 140 t C ns v supply C volts t off (en) t transition figure 8. switching time vs. power supply 280 240 100 25 105 65 85 45 120 t on (en) 220 200 180 160 140 t C ns temperature C 8 c t off (en) t transition 260 v dd = +15v v ss = C15v v in = +5v figure 9. switching time vs. temperature 2000 1000 0 C15 C5 15 5 010 C10 500 1750 1500 1250 750 250 v d (v s ) C volts r on C v +25 8 c v dd = +15v v ss = C15v +105 8 c +85 8 c figure 4. on resistance as a function of v d (v s ) for different temperatures 1m 1 m 1p C50 C30 60 10 C20 20 C40 30 40 C10 0 50 1n 100 m 10 m 10n 100n 10p 100p v s C input voltage C volts i s C input leakage C a operating range v dd = +15v v ss = C15v v d = 0v figure 5. input leakage current as a function of v s (power supplies on) during overvoltage conditions 0.3 0.2 C0.2 C14 C6 14 2 C2 6 C10 0.1 10 0.0 C0.1 v s , v d C volts leakage currents C na i s (off) i d (off) i d (on) v dd = +15v v ss = C15v t a = +25 8 c figure 6. leakage currents as a function of v d (v s )
adg438f/adg439f C6C rev. c n-channel threshold voltage (v tn ). when a voltage more nega- tive than v ss is applied to the multiplexer, the p-channel mosfet will turn off since the analog input is more negative than the difference between v ss and the p-channel threshold voltage (v tp ). when the power supplies are present but the channel is off, again either the p-channel mosfet or one of the n-channel mosfets will remain off when an overvoltage occurs. finally, when the power supplies are off, the gate of each mosfet will be at ground. a negative overvoltage switches on the first n-channel mosfet but the bias produced by the overvoltage causes the p-channel mosfet to remain turned off. with a positive overvoltage, the first mosfet in the series will remain off since the gate to source voltage applied to this mosfet is negative. during fault conditions, the leakage current into and out of the adg438f/adg439f is limited to a few microamps. this pro- tects the multiplexer and succeeding circuitry from over stresses as well as protecting the signal sources which drive the multi- plexer. also, the other channels of the multiplexer will be undisturbed by the overvoltage and will continue to operate normally. q1 q2 q3 +55v overvoltage n-channel mosfet is off figure 12. +55 v overvoltage with power off q1 q2 q3 C40v overvoltage n-channel mosfet is on p-channel mosfet is off figure 13. C40 v overvoltage with power off theory of operation the adg438f/adg439f multiplexers are capable of with- standing overvoltages from C40 v to +55 v, irrespective of whether the power supplies are present or not. each channel of the multiplexer consists of an n-channel mosfet, a p-channel mosfet and an n-channel mosfet, connected in series. when the analog input exceeds the power supplies, one of the mosfets will switch off, limiting the current to sub-microamp levels, thereby preventing the overvoltage from damaging any circuitry following the multiplexer. figure 12 illustrates the channel architecture that enables these multiplexers to with- stand continuous overvoltages. when an analog input of v ss + 1.2 v to v dd C 0.8 v is applied to the adg438f/adg439f, the multiplexer behaves as a standard multiplexer, with specifications similar to a standard multiplexer, for example, the on-resistance is 180 w typically. however, when an overvoltage is applied to the device, one of the three mosfets will turn off. figures 10 to 13 show the conditions of the three mosfets for the various overvoltage situations. when the analog input ap- plied to an on channel approaches the positive power supply line, the n-channel mosfet turns off since the voltage on the analog input exceeds the difference between v dd and the q1 q2 q3 +55v overvoltage n-channel mosfet is off v dd v ss figure 10. +55 v overvoltage input to the on channel q1 q2 q3 C40v overvoltage n-channel mosfet is on v dd v ss p-channel mosfet is off figure 11. C40 v overvoltage on an off channel with multiplexer power on test circuits i ds s r on = v 1 /i ds v1 v s d test circuit 1. on resistance v d s1 s2 s8 v s v ss v dd i d (off) v ss v dd +0.8v d en a test circuit 3. i d (off) v s i s (off) v d s1 s2 s8 v ss v dd v ss v dd +0.8v d en a test circuit 2. i s (off)
adg438f/adg439f C7C rev. c v d s1 s2 s8 v s v ss v dd v ss v dd +0.8v d en a test circuit 5. input leakage current (with overvoltage) v s 0v 0v 0v a * similar connection for adg439f a2 v ss v dd d a1 a0 en gnd adg438f * s1 s8 test circuit 6. input leakage current (with power supplies off) i d (on) v d s1 s8 v s v ss v dd v ss v dd +2.4v d en a s2 test circuit 4. i d (on) 3v 50% v out t transition 90% 90% t transition address drive (v in ) 50% a2 v out v ss v dd d v s1 * similar connection for adg439f a1 a0 en gnd adg438f * s1 s8 s2 thru s7 v in +2.4v 50 v v s8 r l 1m v c l 35pf v ss v dd test circuit 7. switching time of multiplexer, t transition a2 v out v ss v dd d v s * similar connection for adg439f a1 a0 en gnd adg438f * s1 s8 s2 thru s7 v in +2.4v 50 v r l 1k v c l 35pf v ss v dd address drive (v in ) 3v v out t open 80% 80% test circuit 8. break-before-make delay, t open 3v 50% output 0.9v o 50% t on (en) 0.9v o 0v v o 0v t off (en) enable drive (v in ) a2 v out v ss v dd d v s * similar connection for adg439f a1 a0 en gnd adg438f * s1 s2 thru s8 v in 50 v r l 1k v c l 35pf v ss v dd test circuit 9. enable delay, t on (en), t off (en)
adg438f/adg439f C8C rev. c c1992cC0C5/99 printed in u.s.a. v out v ss d * similar connection for adg439f a1 a0 en gnd adg438f * r l 1k v v ss v dd s1 v s s8 a2 v dd test circuit 11. off isolation a2 v out v ss v dd d a1 a0 en gnd adg438f * 1k v v ss v dd s1 v s 2.4v s2 s8 1k v crosstalk = 20 log v out /v in * similar connection for adg439f test circuit 12. channel-to-channel crosstalk outline dimensions dimensions shown in inches and (mm). 16-lead plastic (n-16) 16 1 8 9 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead soic (r-16n) (narrow body) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc
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